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1.发明申请公开(公告)号：US20200218682A1
公开(公告)日：2020-07-09
申请号：US16821289
申请日：2020-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： DongSik CHO , Jeonghoon KIM , Rohitaswa BHATTACHARYA , Jaeshin LEE , Honggi JEONG
IPC: G06F13/40 , G06F13/364
Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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2.发明申请公开(公告)号：US20190087370A1
公开(公告)日：2019-03-21
申请号：US16192019
申请日：2018-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： DongSik CHO , Jeonghoon KIM , Rohitaswa BHATTACHARYA , Jaeshin LEE , Honggi JEONG
IPC: G06F13/40 , G06F13/364
Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US20220310515A1
公开(公告)日：2022-09-29
申请号：US17701097
申请日：2022-03-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeshin LEE , Sunil SHIM , Juyoung LIM
IPC: H01L23/535 , H01L23/532 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a structure including a stack structure including a first stack structure and a second stack structure on the first stack structure; a memory vertical structure penetrating the structure; a support vertical structure including a portion penetrating the structure and including an air gap; and a peripheral contact plug, wherein the first and second stack structures includes interlayer insulating layers and gate layers alternately stacked, a side of the memory vertical structure includes a slope changing portion, the peripheral contact plug includes an upper region disposed on a level higher than an upper surface of an uppermost gate layer, the upper region of the peripheral contact plug includes a first region, a second region and a connection region between the first and second regions, and the connection region has a slope different from a slope of at least one of the first and second regions.
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4.发明申请公开(公告)号：US20180173662A1
公开(公告)日：2018-06-21
申请号：US15899877
申请日：2018-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： DongSik CHO , Jeonghoon KIM , Rohitaswa BHATTACHARYA , Jaeshin LEE , Honggi JEONG
IPC: G06F13/40 , G06F13/364
CPC classification number: G06F13/4004 , G06F13/364 , Y02D10/14 , Y02D10/151
Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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Patent Agency Ranking
公开(公告)号：US20240232004A9
公开(公告)日：2024-07-11
申请号：US18400256
申请日：2023-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungwon JEONG , Moonsang KWON , Younghoi HEO , Jaeshin LEE , Eun JUNG
CPC classification number: G06F11/1004 , G06N20/00
Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
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公开(公告)号：US20240134741A1
公开(公告)日：2024-04-25
申请号：US18400256
申请日：2023-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungwon JEONG , Moonsang KWON , Younghoi HEO , Jaeshin LEE , Eun JUNG
CPC classification number: G06F11/1004 , G06N20/00
Abstract: A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
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7.发明公开公开(公告)号：US20240086354A1
公开(公告)日：2024-03-14
申请号：US18515091
申请日：2023-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： DongSik CHO , Jeonghoon KIM , Rohitaswa BHATTACHARYA , Jaeshin LEE , Honggi JEONG
IPC: G06F13/40 , G06F13/364
CPC classification number: G06F13/4004 , G06F13/364 , Y02D10/00
Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US20210342283A1
公开(公告)日：2021-11-04
申请号：US17376590
申请日：2021-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： DongSik CHO , Jeonghoon KIM , Rohitaswa BHATTACHARYA , Jaeshin LEE , Honggi JEONG
IPC: G06F13/40 , G06F13/364
Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US20210165733A1
公开(公告)日：2021-06-03
申请号：US16913707
申请日：2020-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeshin LEE , Eunhye OH , Jaechul PARK
Abstract: A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.
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