公开(公告)号：US20250105088A1

公开(公告)日：2025-03-27

申请号：US18891644

申请日：2024-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Jaesun Kim

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L25/065 ,  H05K1/18

Abstract: An example semiconductor package includes a first redistribution structure, a first chip on the first redistribution structure, a molding member on the first redistribution structure to surround the first chip, a conductive pillar penetrating the molding member in a vertical direction, a second redistribution structure on the first chip and the molding member, a second chip on the second redistribution structure, and a third chip on the second redistribution structure and separated from the second chip in a horizontal direction. The first redistribution structure includes a first redistribution insulating layer and a first redistribution pattern. The second redistribution structure includes a second redistribution insulating layer and a second redistribution pattern. The first chip includes a first semiconductor substrate and a through electrode penetrating the first semiconductor substrate in the vertical direction. The through electrode is in contact with the second redistribution pattern.

公开(公告)号：US20240128172A1

公开(公告)日：2024-04-18

申请号：US18235596

申请日：2023-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inwon O ,  Jaesun Kim ,  Yunseok Choi

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate including a ball pad with first and second pads, a wiring line extending between the first and second pads, and a solder mask layer including a first opening exposing a portion of the first pad and a second opening exposing a portion of the second pad, and a semiconductor chip on an upper surface of the package substrate, and a connection bump on a lower surface of the ball pad and connected to the first and second pads. The connection bump covers a lower surface and a first side surface of the first pad exposed through the first opening, a lower surface and side surfaces of a region of the solder mask layer covering the wiring line, and a lower surface and a first side surface of the second pad exposed through the second opening.

公开(公告)号：US20250132277A1

公开(公告)日：2025-04-24

申请号：US18801963

申请日：2024-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokbeom Yong ,  Jaesun Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes a lower redistribution structure, a lower semiconductor chip on the lower redistribution structure, and an upper redistribution structure t on the lower semiconductor chip and including a signal pad, a power pad, a grounding plane, and an upper insulation layer, where the signal pad, the power pad, and the grounding plane are in the upper insulation layer, where a distance between the signal pad and the lower redistribution structure in a vertical direction is less than a distance between the power pad and the lower redistribution structure in the vertical direction, and where the vertical direction is perpendicular to an upper surface of the lower redistribution structure.

公开(公告)号：US20250054846A1

公开(公告)日：2025-02-13

申请号：US18633688

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesun Kim ,  Kwangsoo Kim ,  Yiseul Han

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: Provided is a semiconductor package having a multi-chip package structure including a lower semiconductor chip and an upper semiconductor chip. The upper semiconductor chip includes a plurality of upper semiconductor chips, and one of the plurality of upper semiconductor chips is integrally connected to an adjacent one of the plurality of upper semiconductor chips with a scribe lane therebetween on a same plane.