公开(公告)号：US20240128172A1

公开(公告)日：2024-04-18

申请号：US18235596

申请日：2023-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inwon O ,  Jaesun Kim ,  Yunseok Choi

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate including a ball pad with first and second pads, a wiring line extending between the first and second pads, and a solder mask layer including a first opening exposing a portion of the first pad and a second opening exposing a portion of the second pad, and a semiconductor chip on an upper surface of the package substrate, and a connection bump on a lower surface of the ball pad and connected to the first and second pads. The connection bump covers a lower surface and a first side surface of the first pad exposed through the first opening, a lower surface and side surfaces of a region of the solder mask layer covering the wiring line, and a lower surface and a first side surface of the second pad exposed through the second opening.

公开(公告)号：US11094636B2

公开(公告)日：2021-08-17

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Inwon O ,  Jongyoun Kim ,  Seokhyun Lee ,  Yeonho Jang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

公开(公告)号：US20240321826A1

公开(公告)日：2024-09-26

申请号：US18402883

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul YANG ,  Inwon O

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/181

Abstract: A semiconductor package includes a first redistribution substrate; a first semiconductor chip on the first redistribution substrate; a second redistribution substrate on the first semiconductor chip; inter-substrate through-electrodes on the first redistribution substrate at one side of the first semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate; a second semiconductor chip on the first semiconductor chip; and a heat dissipation structure on the second semiconductor chip.