公开(公告)号：US20220149048A1

公开(公告)日：2022-05-12

申请号：US17357139

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonkyu RHEE ,  Jiyoung AHN ,  Hyunyong KIM ,  Jamin KOO ,  Yongseok AHN ,  Minsub UM ,  Sangho LEE ,  Yoonyoung CHOI

IPC: H01L27/108

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

公开(公告)号：US20160365279A1

公开(公告)日：2016-12-15

申请号：US15060641

申请日：2016-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jamin KOO ,  Youngseok KIM ,  Kongsoo LEE ,  Goeun BAE

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76895 ,  H01L21/28035 ,  H01L21/288 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53271 ,  H01L27/10888

Abstract: Provided is a method of fabricating a semiconductor device, the method including forming interconnection structures extending parallel to each other on a substrate; performing a coating process and forming a liquid state silicon source material layer filling an area between the interconnection structures; performing a first annealing process, curing the liquid state silicon source material layer, and forming an amorphous silicon layer; and crystallizing the amorphous silicon layer and forming contact plugs.

Abstract translation: 提供一种制造半导体器件的方法，该方法包括在衬底上形成彼此平行延伸的互连结构; 执行涂覆工艺并形成填充所述互连结构之间的区域的液态硅源材料层; 进行第一退火处理，固化液态硅源材料层，形成非晶硅层; 并使非晶硅层结晶并形成接触塞。

公开(公告)号：US20220115377A1

公开(公告)日：2022-04-14

申请号：US17331725

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyokyoung KIM ,  Jamin KOO ,  Jonghyeok KIM ,  Daeyoung MOON

IPC: H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.

公开(公告)号：US20230422487A1

公开(公告)日：2023-12-28

申请号：US18149800

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok KIM ,  Jamin KOO ,  Beom Seo KIM ,  Wonseok YOO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.

公开(公告)号：US20230209805A1

公开(公告)日：2023-06-29

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin KOO ,  Kyuwan KIM ,  Kisoo PARK

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.