THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    1.
    发明申请

    公开(公告)号:US20190312054A1

    公开(公告)日:2019-10-10

    申请号:US16239130

    申请日:2019-01-03

    Abstract: A three-dimensional semiconductor device and method of fabrication is provided. The three-dimensional semiconductor device includes a stacked structure on a lower structure. The stacked structure includes interlayer insulating layers and gate electrodes. The device also includes a channel structure on the lower structure, with the channel structure including a horizontal portion between the stacked structure and the lower structure. The channel structure also includes a plurality of vertical portions extended in a vertical direction. The device also includes support patterns on the lower structure. In addition, the device includes a gate dielectric structure having a lower portion and upper portions. The method of fabrication includes forming the stacked structure with holes. The method also includes removing a sacrificial layer from a horizontal area above the lower structure and forming a channel structure within the holes and within a horizontal space made by removal of the sacrificial layer.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

    公开(公告)号:US20210143176A1

    公开(公告)日:2021-05-13

    申请号:US17152883

    申请日:2021-01-20

    Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

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