公开(公告)号：US20180254271A1

公开(公告)日：2018-09-06

申请号：US15723669

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Woo ,  Jang Gn YUN ,  Joon Sung LIM ,  Sung Min HWANG

IPC: H01L27/07 ,  H01L23/00 ,  H01L49/02 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/43

CPC classification number: H01L27/0738 ,  H01L21/31051 ,  H01L21/76895 ,  H01L24/06 ,  H01L28/24 ,  H01L29/435 ,  H01L29/4983

Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

公开(公告)号：US20200176464A1

公开(公告)日：2020-06-04

申请号：US16512513

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon Jang ,  Woo Sung YANG ,  Joon Sung LIM ,  Sung Min HWANG

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.