公开(公告)号：US20200350326A1

公开(公告)日：2020-11-05

申请号：US16668222

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn YUN ,  Jaeduk LEE

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US20240284686A1

公开(公告)日：2024-08-22

申请号：US18444874

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Hyunho KIM ,  Jaebok BAEK ,  Janggn YUN ,  Jeehoon HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Provided is an integrated circuit device with increased electrical reliability by forming an ohmic junction between a contact structure and a wiring line by bypassing a common source line such that the common source line, to which a common source line driver is connected, is electrically connected to the contact structure through the wiring line.

公开(公告)号：US20240260270A1

公开(公告)日：2024-08-01

申请号：US18508530

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoon HONG ,  Janggn YUN ,  Hyunho KIM ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: A field effect transistor includes a horizontal channel layer, an interlayer insulating layer on the horizontal channel layer, a gate electrode layer on the interlayer insulating layer, a first vertical channel structure passing through the gate electrode layer and the interlayer insulating layer in a vertical direction, in contact with the horizontal channel layer, and connected to one of a source terminal or a drain terminal, and a second vertical channel structure apart from the first vertical channel structure in a horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction, in contact with the horizontal channel layer, and connected to another of the source terminal or the drain terminal.

公开(公告)号：US20210143172A1

公开(公告)日：2021-05-13

申请号：US17036034

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn YUN ,  Jaeduk LEE ,  Dongwhee KWON

IPC: H01L27/11582 ,  H01L27/24 ,  H01L27/11556 ,  H01L23/535

Abstract: A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.