公开(公告)号：US20240234551A1

公开(公告)日：2024-07-11

申请号：US18539355

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangwoo PARK ,  DONGWOO KIM ,  JINBUM KIM

IPC: H01L29/732 ,  H01L23/522

CPC classification number: H01L29/732 ,  H01L23/522 ,  H01L29/0673

Abstract: A semiconductor device includes first, second, and third epitaxial layers sequentially stacked on a substrate and a first diffusion prevention layer provided in at least one of regions between the first and second epitaxial layers and between the second and third epitaxial layers. The first and third epitaxial layers have a first conductivity type, and the second epitaxial layer has a second conductivity type. The first diffusion prevention layer is configured to prevent an impurity in the second epitaxial layer from being diffused. The first, second, and third epitaxial layers include first, second, and third active patterns, respectively, which are respective provided in upper portions thereof and on collector, base, and emitter regions, respectively, of the substrate.

公开(公告)号：US20240203989A1

公开(公告)日：2024-06-20

申请号：US18227064

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Youngkwang KIM ,  Chanyoung KIM ,  Jangwoo PARK ,  Sangmoon LEE ,  Sujin JUNG

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region, a first active pattern on the PMOSFET region, a second active pattern on the NMOSFET region, a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern, a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern, and a gate electrode on the first channel pattern and the second channel pattern.