公开(公告)号：US20230422479A1

公开(公告)日：2023-12-28

申请号：US18133964

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.