公开(公告)号：US20230328964A1

公开(公告)日：2023-10-12

申请号：US18089956

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng Lee ,  Sangwoo Pae ,  Namhyun Lee

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor device includes a first fin pattern protruding from a substrate and extending in a first direction; first and second active layers extending in the first direction on the first fin pattern, the second active layer being at a level higher than a level of the first active layer, the first and second active layers forming a first active layer structure; a first gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, and extending in a second direction; and a second gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, extending in the second direction, and disposed to be parallel to the first gate. The first active layer includes a first region extending from a first overlapping region of the first active layer overlapping the first gate by a first length in a direction away from the second gate, and the second active layer includes a first region extending from a first overlapping region of the second active layer overlapping the first gate by a second length in a direction away from the second gate, the second length shorter than the first length.

公开(公告)号：US20230101075A1

公开(公告)日：2023-03-30

申请号：US17748291

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonhaeng Lee ,  Gangjun Kim

IPC: H01L23/525 ,  H01L23/528 ,  H01L29/66 ,  H01L21/28

Abstract: A transistor includes: a gate structure disposed on a substrate, and including a gate insulation layer and a gate electrode; a first impurity region disposed at an upper portion of a substrate and adjacent to a first sidewall of the gate structure; a second impurity region disposed at an upper portion of the substrate and adjacent to a second sidewall opposite to the first sidewall of the gate structure; and a first threshold voltage controlling line spaced apart from the substrate, wherein the first threshold voltage controlling line faces at least a portion of the first impurity region, wherein the first threshold voltage controlling line includes a conductive material, and wherein the first threshold voltage controlling line extends in a direction that crosses a direction in which the first impurity region extends.

公开(公告)号：US20230422479A1

公开(公告)日：2023-12-28

申请号：US18133964

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.