公开(公告)号：US09595315B2

公开(公告)日：2017-03-14

申请号：US14734315

申请日：2015-06-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Joon Han ,  Won-Kyung Park ,  Junhee Lim ,  Sungho Jang

IPC分类号： G11C11/4091 ,  G11C5/02 ,  G11C11/4094

CPC分类号： G11C11/4091 ,  G11C5/02 ,  G11C11/4094 ,  G11C2207/002

摘要： A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

摘要翻译： 半导体存储器件包括位线读出放大器，第一列选择栅极和第二列选择栅极。 在存储器单元的感测操作期间，位线读出放大器感测位线和互补位线之间的电位差。 第一列选择栅极基于列选择信号将位线上的电位传送到本地读出放大器。 第二列选择栅极基于列选择信号将互补位线上的电位传送到本地读出放大器。 第一和第二列选择栅极具有不同的电流驱动能力，以补偿位线互连电阻的差异。

公开(公告)号：US09082647B2

公开(公告)日：2015-07-14

申请号：US14465982

申请日：2014-08-22

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Ho Jang ,  Dong-Jin Lee ,  Bong-Soo Kim ,  Jun-Hee Lim ,  Joon Han

IPC分类号： H01L27/108 ,  H01L27/12 ,  H01L27/13

CPC分类号： H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/12 ,  H01L27/13 ,  H01L29/785

摘要： There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

摘要翻译： 提供了一种半导体器件。 半导体器件可以包括多个触点插头，绝缘层图案，金属氧化物层图案，金属图案和金属线。 接触插头接触基板。 绝缘层图案形成在接触插塞之间，并且具有比接触插塞低的顶表面。 金属氧化物层图案形成在绝缘层图案上，并且具有比氧化硅更高的介电常数。 金属图案形成在金属氧化物层图案上并接触接触插塞的侧壁。 金属线接触接触插塞的顶表面和金属图案并在其上延伸。

公开(公告)号：US11437089B2

公开(公告)日：2022-09-06

申请号：US17245334

申请日：2021-04-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

IPC分类号： G11C11/4091 ,  H01L27/108

摘要： An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

公开(公告)号：US10930740B2

公开(公告)日：2021-02-23

申请号：US16546506

申请日：2019-08-21

申请人： Samsung Electronics Co., Ltd.

发明人： Hae-in Jung ,  Moon-young Jeong ,  Joon Han ,  Satoru Yamada

IPC分类号： H01L29/10 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L27/11573 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/306 ,  H01L27/11526 ,  H01L27/088

摘要： Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

公开(公告)号：US20230422479A1

公开(公告)日：2023-12-28

申请号：US18133964

申请日：2023-04-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/34 ,  H10B12/482

摘要： A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.