公开(公告)号：US20180357005A1

公开(公告)日：2018-12-13

申请号：US15869393

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ho LEE ,  Ho-jun SHIM ,  Won Woo RO ,  Won Seob JEONG ,  Myung Kuk YOON ,  Won JEON

IPC: G06F3/06 ,  G06F17/30 ,  G06K9/62

Abstract: Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.

公开(公告)号：US20200073799A1

公开(公告)日：2020-03-05

申请号：US16445005

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ho LEE ,  Young-sik KIM ,  Eun-chu OH ,  Young-kwang YOO ,  Young-geun LEE

IPC: G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F12/02

Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.

公开(公告)号：US20200159619A1

公开(公告)日：2020-05-21

申请号：US16415906

申请日：2019-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu OH ,  Jeong-ho LEE ,  Young-jin CHO

IPC: G06F11/10 ,  G11C13/00 ,  G11C29/52

Abstract: Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.