公开(公告)号：US20200073799A1

公开(公告)日：2020-03-05

申请号：US16445005

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ho LEE ,  Young-sik KIM ,  Eun-chu OH ,  Young-kwang YOO ,  Young-geun LEE

IPC: G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F12/02

Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.

公开(公告)号：US20190051353A1

公开(公告)日：2019-02-14

申请号：US16161285

申请日：2018-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-chu OH ,  Pil-sang Yoon ,  Jun-jin Kong ,  Hong-rak Son

IPC: G11C13/00 ,  H03M13/27 ,  H03M13/05 ,  G06F12/00 ,  G11C8/06 ,  G06F11/10

CPC classification number: G11C13/0069 ,  G06F11/1048 ,  G06F12/00 ,  G06F12/0238 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C8/06 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2213/72 ,  H03M13/05 ,  H03M13/27

Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

公开(公告)号：US20130198577A1

公开(公告)日：2013-08-01

申请号：US13648421

申请日：2012-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-chu OH ,  Jae-hong KIM ,  Jun-jin KONG

IPC: H03M13/05

CPC classification number: H03M13/05 ,  H03M13/1102 ,  H03M13/356 ,  H03M13/3707

Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

Abstract translation: 存储器系统包括错误检查和校正（ECC）引擎，其被配置为根据第一方法执行临时存储在第一存储器阵列中的数据的错误校验和校正以及从第一存储器阵列读出的数据，并执行错误校验和校正 根据第二方法从第一存储器阵列读出并从第二存储器阵列读出的数据中存储在第二存储器阵列中的数据，其中响应于至少具有至少一个控制信号的控制信号选择第一方法和第二方法 第一种逻辑级别，第二种方法检查和纠正以比较第一种方法更高速率发生的数据错误。