公开(公告)号：US20170062211A1

公开(公告)日：2017-03-02

申请号：US15209093

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin LIM ,  Gi-gwan PARK ,  Sang-yub IE ,  Jong-han LEE ,  Jeong-hyuk YIM ,  Hye-ri HONG

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/02123 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/3003 ,  H01L21/67207 ,  H01L29/66795

Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

Abstract translation: 提供制造半导体器件的方法。 所述方法可以包括形成从衬底突出的鳍状有源区，并形成覆盖鳍状有源区的顶表面和两个侧壁的栅极绝缘膜。 栅极绝缘膜可以包括高k电介质膜。 所述方法还可以包括在栅绝缘膜上形成含金属层，在含金属层上形成含有氢原子的硅封盖层，去除硅封盖层中所含的一部分氢原子，除去硅封盖 层和所述含金属层的至少一部分，并且在所述栅极绝缘膜上形成栅电极。 栅电极可以覆盖翅片型有源区的顶表面和两个侧壁。

公开(公告)号：US20190148226A1

公开(公告)日：2019-05-16

申请号：US16154896

申请日：2018-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-hyuk YIM ,  Kuo Tai HUANG ,  Wan-don KIM ,  Sang-jin HYUN

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/417 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.