公开(公告)号：US20240339331A1

公开(公告)日：2024-10-10

申请号：US18143076

申请日：2023-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/02123 ,  H01L21/308 ,  H01L29/785 ,  H01L29/41791

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region, forming a first gate structure and a second gate structure on the MV region and a second gate structure on the LV region, forming a patterned mask on the MV region as the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure, and then forming a first epitaxial layer between the first gate structure and the second gate structure.

公开(公告)号：US20240339316A1

公开(公告)日：2024-10-10

申请号：US18746799

申请日：2024-06-18

Applicant: Applied Materials, Inc.

Inventor： Aykut AYDIN ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Abhijit Basu MALLICK ,  Takehito KOSHIZAWA ,  Bo QI

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02211 ,  H01L21/02271

Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

公开(公告)号：US20240178070A1

公开(公告)日：2024-05-30

申请号：US18433162

申请日：2024-02-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02123 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66545

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

公开(公告)号：US20240162035A1

公开(公告)日：2024-05-16

申请号：US18097285

申请日：2023-01-16

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Shou-Zen Chang ,  Chun-Lin Lu

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/02 ,  H01L29/68

CPC classification number: H01L21/02123 ,  H01L21/02175 ,  H01L21/76816 ,  H01L24/05 ,  H01L24/29 ,  H01L27/0225 ,  H01L29/685 ,  H01L2224/05085 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184

Abstract: A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

公开(公告)号：US11923188B2

公开(公告)日：2024-03-05

申请号：US17025388

申请日：2020-09-18

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Takeo Hanashima

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  H01L21/67

CPC classification number: H01L21/02123 ,  C23C16/455 ,  C23C16/4584 ,  H01L21/67161

Abstract: There is included providing a substrate in a process chamber; and forming a film on the substrate in the process chamber by supplying an inert gas from a first supplier, supplying a first processing gas from a second supplier, and supplying an inert gas from a third supplier to the substrate, the third supplier being installed at an opposite side of the first supplier with respect to a straight line that passes through the second supplier and a center of the substrate and is interposed between the first supplier and the third supplier, to the substrate, wherein in the film, a substrate in-plane film thickness distribution of the film is adjusted by controlling a balance between a flow rate of the inert gas supplied from the first supplier and a flow rate of the inert gas supplied from the third supplier.

公开(公告)号：US11915976B2

公开(公告)日：2024-02-27

申请号：US17809109

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Wei Chu ,  Ying-Chi Su ,  Yu-Kai Chen ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/02068 ,  H01L21/02123 ,  H01L21/32053

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

公开(公告)号：US20230366094A1

公开(公告)日：2023-11-16

申请号：US18351681

申请日：2023-07-13

Applicant: Novellus Systems, Inc.

Inventor： Jason Dirk Haverkamp ,  Pramod Subramonium ,  Joseph L. Womack ,  Dong Niu ,  Keith Fox ,  John B. Alexy ,  Patrick G. Breiling ,  Jennifer L. Petraglia ,  Mandyam A. Sriram ,  George Andrew Antonelli ,  Bart J. van Schravendijk

IPC: C23C16/50 ,  H01J37/32 ,  C23C16/455 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/52 ,  C23C16/509 ,  H01L21/67 ,  H01L21/02 ,  C23C16/24 ,  C23C16/54

CPC classification number: C23C16/50 ,  H01J37/32137 ,  C23C16/45565 ,  H01J37/32155 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4401 ,  C23C16/45574 ,  C23C16/52 ,  C23C16/509 ,  H01L21/67207 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/67201 ,  C23C16/24 ,  C23C16/54 ,  H01L21/6719 ,  H01L21/02123 ,  H01L21/022 ,  C23C16/45512 ,  H01L21/02274

Abstract: An apparatus for depositing film stacks in-situ (i.e., without a vacuum break or air exposure) are described. In one example, a plasma-enhanced chemical vapor deposition apparatus configured to deposit a plurality of film layers on a substrate without exposing the substrate to a vacuum break between film deposition phases, is provided. The apparatus includes a process chamber, a plasma source and a controller configured to control the plasma source to generate reactant radicals using a particular reactant gas mixture during the particular deposition phase, and sustain the plasma during a transition from the particular reactant gas mixture supplied during the particular deposition phase to a different reactant gas mixture supplied during a different deposition phase.

公开(公告)号：US20230360906A1

公开(公告)日：2023-11-09

申请号：US17737328

申请日：2022-05-05

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Susmit Singha Roy ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02211 ,  H01L21/02532 ,  H01L21/02123 ,  H01L21/0234 ,  H01L21/31111 ,  H01L29/42392

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the oxygen-containing precursor at a temperature less than or about 700° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.

公开(公告)号：US20190252328A1

公开(公告)日：2019-08-15

申请号：US16390877

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Clinton Chao ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L23/52 ,  H01L21/56 ,  H01L21/78 ,  H01L21/302 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L23/562 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/32051 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/52 ,  H01L23/585 ,  H01L24/05 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

公开(公告)号：US20190214503A1

公开(公告)日：2019-07-11

申请号：US16045125

申请日：2018-07-25

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.

Inventor： MingJiue YU ,  YuanJun HSU

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L23/532 ,  H01L21/02 ,  H01L21/48

CPC classification number: H01L29/78618 ,  H01L21/02123 ,  H01L21/02304 ,  H01L21/486 ,  H01L23/5329 ,  H01L27/3258 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742

Abstract: A P-type thin-film transistor and manufacturing method are provided. The method includes: forming an active layer having a P-type material on a buffering layer; forming a gate insulation layer on the active layer; depositing a gate metal layer on the gate insulation layer; forming a photoresist layer on the gate metal layer, and patterning the photoresist layer; etching the gate metal layer to form a gate electrode such that a projection of the gate electrode is within the patterned photoresist layer; using the patterned photoresist layer as a barrier layer to etch the gate insulation layer such that a projection of the gate electrode is within the gate insulation layer, and a projection of the gate insulation layer is within the active layer; doping two side regions of the active layer located below the gate insulation layer; and forming a source electrode and drain electrode on the doped regions.