公开(公告)号：US20230361804A1

公开(公告)日：2023-11-09

申请号：US18105815

申请日：2023-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Taeryeong KIM ,  Seongook JUNG ,  Jeonghyeok YOU

IPC: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/24

CPC classification number: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/2472 ,  H03K2005/00078

Abstract: A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.

公开(公告)号：US20250104751A1

公开(公告)日：2025-03-27

申请号：US18647853

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jeonghyeok YOU ,  Seong-Ook JUNG ,  Ji Young KIM ,  Hohyun CHAE

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/50

Abstract: A memory device includes core dies including memory cell arrays, and a buffer die electrically connected to the core dies through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates data strobe signals based on the external clock signal for communicating data with the core dies, a DQS calibration circuit that detects a latency of each of plural rank signal that are received from the core dies based on the data strobe signals, respectively, and a coefficient decision circuit that detects a threshold voltage code of the buffer die, applies a weight to the latency of each rank signal based on the threshold voltage code to generate a weighted calibration code for each rank signal, and transmits the weighted calibration codes to respective ones of the core dies.

公开(公告)号：US20240146498A1

公开(公告)日：2024-05-02

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Jeonghyeok YOU ,  Seongook JUNG ,  Taeryeong KIM ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14

CPC classification number: H04L7/0016 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.