公开(公告)号：US20230361804A1

公开(公告)日：2023-11-09

申请号：US18105815

申请日：2023-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Taeryeong KIM ,  Seongook JUNG ,  Jeonghyeok YOU

IPC: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/24

CPC classification number: H04B1/40 ,  H03K19/20 ,  H03K3/037 ,  H03K5/14 ,  H03K5/2472 ,  H03K2005/00078

Abstract: A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.

公开(公告)号：US20240146498A1

公开(公告)日：2024-05-02

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYONGMO MOON ,  Jeonghyeok YOU ,  Seongook JUNG ,  Taeryeong KIM ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14

CPC classification number: H04L7/0016 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

公开(公告)号：US20220069822A1

公开(公告)日：2022-03-03

申请号：US17353917

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jiyoung KIM ,  Seongook JUNG ,  Jongsoo LEE

IPC: H03K19/173 ,  H03K19/0175 ,  H03K19/017 ,  H03K19/17788 ,  G11C7/14 ,  G11C7/22

Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.