公开(公告)号：US11158550B2

公开(公告)日：2021-10-26

申请号：US16877838

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongjoon Oh

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

公开(公告)号：US11862603B2

公开(公告)日：2024-01-02

申请号：US17001978

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewook Kim ,  Jongho Lee ,  Jeongjoon Oh ,  Hyeon Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

公开(公告)号：US20210159213A1

公开(公告)日：2021-05-27

申请号：US17001978

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewook Kim ,  Jongho Lee ,  Jeongjoon Oh ,  Hyeon Hwang

IPC: H01L25/065

Abstract: A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

公开(公告)号：US11670556B2

公开(公告)日：2023-06-06

申请号：US17448769

申请日：2021-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongjoon Oh

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L2224/214 ,  H01L2224/48227

Abstract: A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

公开(公告)号：US20210125882A1

公开(公告)日：2021-04-29

申请号：US16877838

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongjoon Oh

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.