公开(公告)号：US20230178439A1

公开(公告)日：2023-06-08

申请号：US17950512

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun LEE ,  Hyojung NOH ,  Minwoo SONG ,  Yongho HA ,  Jeongwon HWANG

IPC: H01L21/8234 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L21/823493 ,  H01L21/823462 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0623

Abstract: A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes an forming a trench in a substrate, forming a gate dielectric layer on the trench, forming a gate layer on the gate dielectric layer, and annealing the gate dielectric layer and the gate layer, wherein, after the first annealing operation, the gate layer includes a molybdenum-tantalum alloy.

公开(公告)号：US20240421070A1

公开(公告)日：2024-12-19

申请号：US18409491

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunjung LEE ,  Sanghoon AHN ,  Donggon YOO ,  Jangeun LEE ,  Jeongwon HWANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.