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1.发明申请公开(公告)号：US20180204621A1
公开(公告)日：2018-07-19
申请号：US15919155
申请日：2018-03-12
发明人： Yoon Kim , Dong-chan Kim , Ji-sang Lee
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/107 , G11C16/349
摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.
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2.发明授权公开(公告)号：US10699788B2
公开(公告)日：2020-06-30
申请号：US16108323
申请日：2018-08-22
发明人： Ji-sang Lee
IPC分类号： G11C16/14 , G11C16/08 , G11C16/24 , G11C16/26 , G11C11/56 , G11C16/34 , G11C16/10 , G11C16/04
摘要： An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.
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公开(公告)号：US10224109B2
公开(公告)日：2019-03-05
申请号：US15919155
申请日：2018-03-12
发明人： Yoon Kim , Dong-chan Kim , Ji-sang Lee
摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.
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公开(公告)号：US11158381B2
公开(公告)日：2021-10-26
申请号：US17025281
申请日：2020-09-18
发明人： Ji-sang Lee
IPC分类号： G11C16/14 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/34 , G11C16/04
摘要： An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.
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公开(公告)号：US10957397B2
公开(公告)日：2021-03-23
申请号：US16881779
申请日：2020-05-22
发明人： Ji-sang Lee
IPC分类号： G11C16/14 , G11C16/08 , G11C16/24 , G11C16/26 , G11C11/56 , G11C16/34 , G11C16/10 , G11C16/04
摘要： An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.
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