公开(公告)号：US20190311954A1

公开(公告)日：2019-10-10

申请号：US16450383

申请日：2019-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  Jin Tae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

IPC: H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  G06F17/50

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US20170294430A1

公开(公告)日：2017-10-12

申请号：US15298586

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo SEO ,  Jin Tae KIM ,  Tae Joong SONG ,  Hyoung-Suk OH ,  Keun Ho LEE ,  Dal Hee LEE ,  Sung We CHO

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/177 ,  H01L21/67 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.