-
公开(公告)号：US20200076410A1
公开(公告)日：2020-03-05
申请号：US16679794
申请日：2019-11-11
Inventor： Jae-Woo SEO , Youngsoo Shin , Jinwook Jung
IPC: H03K3/3562 , G01R31/3185 , H01L27/02 , G01R31/317
Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.
-
2.发明申请公开(公告)号：US20170294430A1
公开(公告)日：2017-10-12
申请号：US15298586
申请日：2016-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Woo SEO , Jin Tae KIM , Tae Joong SONG , Hyoung-Suk OH , Keun Ho LEE , Dal Hee LEE , Sung We CHO
IPC: H01L27/02 , H01L23/528 , H03K19/177 , H01L21/67 , H01L21/8234 , H01L23/522 , H01L27/088
Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.
-
3.发明申请公开(公告)号：US20190311954A1
公开(公告)日：2019-10-10
申请号：US16450383
申请日：2019-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young KIM , Jin Tae KIM , Jae-Woo SEO , Dong-yeon HEO
IPC: H01L21/8234 , H01L27/02 , H01L21/768 , G06F17/50
Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
-
公开(公告)号：US20170004324A1
公开(公告)日：2017-01-05
申请号：US15010738
申请日：2016-01-29
Inventor： Jae-Woo SEO , Jung-Hee CHEON , Mi-Ran KIM , Myung-Sun KIM
CPC classification number: G06F21/6227 , H04L9/008 , H04L9/0618
Abstract: A method for managing data by an electronic device is provided. The method includes receiving first data inputted from a user, generating second data by encrypting the first data using a public key, generating a query comprising the second data, transmitting the query to a server, receiving third data corresponding to the query from the server, generating fourth data by decrypting the third data using a secret key corresponding to the public key, and outputting the fourth data.
Abstract translation: 提供了一种通过电子设备管理数据的方法。 该方法包括接收从用户输入的第一数据，通过使用公钥加密第一数据产生第二数据，生成包括第二数据的查询，将查询发送到服务器，从服务器接收与查询对应的第三数据， 通过使用与该公开密钥相对应的秘密密钥对第三数据进行解密来生成第四数据，并输出第四数据。
-
5.发明申请公开(公告)号：US20200185414A1
公开(公告)日：2020-06-11
申请号：US16791964
申请日：2020-02-14
Inventor： Jae-Woo SEO , Youngsoo SHIN
IPC: H01L27/118 , H01L27/02 , H01L23/528 , G06F30/394
Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
-
Patent Agency Ranking
公开(公告)号：US20180254287A1
公开(公告)日：2018-09-06
申请号：US15908253
申请日：2018-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Woo SEO , Youngsoo SHIN
IPC: H01L27/118 , H01L23/528 , H01L27/02 , G06F17/50
Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
-
公开(公告)号：US20210313310A1
公开(公告)日：2021-10-07
申请号：US17158109
申请日：2021-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji Su YU , Jae-Woo SEO , Sanghoon BAEK , Hyeon Gyu YOU
IPC: H01L27/02 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392
Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.
-
8.发明申请公开(公告)号：US20150205901A1
公开(公告)日：2015-07-23
申请号：US14521928
申请日：2014-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Tae KIM , Jae-Woo SEO
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5068
Abstract: According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.
Abstract translation: 根据示例实施例，布局设计系统包括处理器，被配置为存储标准单元设计的存储模块和生成模块。 标准电池设计包括有源区域和有源区域上的正常栅极区域。 生成模块被配置为接收标准单元设计，以调整横跨标准单元设计的有效区域的主动切割设计的宽度，并且使用处理器输出包括设计元素的芯片设计。 设计元素包括具有调整宽度的主动切割设计。
-
公开(公告)号：US20190207593A1
公开(公告)日：2019-07-04
申请号：US16103233
申请日：2018-08-14
Inventor： Jae-Woo SEO , Youngsoo Shin , Jinwook Jung
IPC: H03K3/3562 , H03K3/037 , G01R31/3185 , H01L27/02 , G01R31/317
Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.
-
10.发明申请公开(公告)号：US20170287787A1
公开(公告)日：2017-10-05
申请号：US15624039
申请日：2017-06-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young KIM , JinTae KIM , Jae-Woo SEO , Dong-yeon HEO
IPC: H01L21/8234 , G06F17/50 , H01L21/768 , H01L27/02 , H01L21/8238 , H01L27/06
CPC classification number: H01L21/823475 , G06F17/5072 , G06F17/5081 , H01L21/76816 , H01L21/76892 , H01L21/823871 , H01L27/0207 , H01L27/0629
Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.014 seconds)
