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公开(公告)号:US20230096434A1
公开(公告)日:2023-03-30
申请号:US17704177
申请日:2022-03-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinduck PARK , Chansik KWON , Yongseong KIM , Inwook IM , Jiyeon HAN
IPC: H01L23/00 , H01L23/522 , H01L23/528
Abstract: A semiconductor chip includes a semiconductor substrate including a device region, and an edge region surrounding the device region, a device layer on the semiconductor substrate, a wiring layer on the device layer, a side surface of the wiring layer at least partially defining a recessed region that is in the edge region such that the side surface of the wiring layer is exposed by the recessed region, and an upper insulating layer on the wiring layer. The recessed region extends from a side surface of the device layer toward the device region. A first portion of the upper insulating layer covers the side surface of the wiring layer that is exposed by the recessed region.
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公开(公告)号:US20210141014A1
公开(公告)日:2021-05-13
申请号:US16916679
申请日:2020-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chansik KWON , Junyoung KO , Jongkeun MOON , Jinduck PARK , Jiyeon HAN
Abstract: A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.
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