公开(公告)号：US20230385497A1

公开(公告)日：2023-11-30

申请号：US18061636

申请日：2022-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Ok Kim ,  Jingon Lee ,  Mijeong Lim

IPC: G06F30/3315

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.