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    METHOD AND SYSTEM OF DESIGNING INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD AND SYSTEM OF DESIGNING INTEGRATED CIRCUIT 有权

    公开(公告)号：US20240378363A1

    公开(公告)日：2024-11-14

    申请号：US18534390

    申请日：2023-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Ok Kim ,  Yongjin Hong ,  Mijeong Lim

    IPC: G06F30/3947

    Abstract: An example embodiment provides a design method of an integrated circuit, including: placing a through-via; determining a keep-out zone around the through-via based on a saturated current variation rate according to a distance from the through-via; placing standard cells; determining a cell placed within the keep out zone among the cells; and setting a timing margin based on the distance from the through-via to the cell.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT INCLUDING SWITCH CELL
    3.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT INCLUDING SWITCH CELL 有权

    公开(公告)号：US20250157990A1

    公开(公告)日：2025-05-15

    申请号：US18784270

    申请日：2024-07-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongjin Hong ,  Ki-Ok Kim

    IPC: H01L25/065

    Abstract: A three-dimensional integrated circuit may include a first switch cell located on a first substrate within a first die among a plurality of stacked dies, and configured to output a virtual power voltage based on a power voltage received from the outside, a first interface module located on the first substrate, and configured to enter an active mode based on the virtual power voltage, and a second interface module located on a second substrate within a second die bonded to the first die among a plurality of dies, and configured to enter the active mode together with the first interface module based on the virtual power voltage.

    TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT
    4.
    发明公开
    TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230385497A1

    公开(公告)日：2023-11-30

    申请号：US18061636

    申请日：2022-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Ok Kim ,  Jingon Lee ,  Mijeong Lim

    IPC: G06F30/3315

    CPC classification number: G06F30/3315 ,  G06F2119/12

    Abstract: A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.

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