公开(公告)号：US10978113B2

公开(公告)日：2021-04-13

申请号：US16738598

申请日：2020-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Chun

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074

Abstract: A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

公开(公告)号：US11869579B2

公开(公告)日：2024-01-09

申请号：US17530911

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Kang ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C11/4093 ,  G11C11/406 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C7/1039 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/40615

Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

公开(公告)号：US12002518B2

公开(公告)日：2024-06-04

申请号：US17710283

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho ,  Kyoman Kang ,  Minhwi Kim ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.

公开(公告)号：US20230055963A1

公开(公告)日：2023-02-23

申请号：US17710283

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung CHO ,  Kyoman Kang ,  Minhwi Kim ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.

公开(公告)号：US11568905B2

公开(公告)日：2023-01-31

申请号：US17200246

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Chun

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074

Abstract: A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.