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公开(公告)号：US11868647B2
公开(公告)日：2024-01-09
申请号：US17522578
申请日：2021-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngdeok Seo , Jinyoung Kim , Sehwan Park , Ilhan Park
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.
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公开(公告)号：US11556415B2
公开(公告)日：2023-01-17
申请号：US17397321
申请日：2021-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan Park , Jinyoung Kim , Ilhan Park , Youngdeok Seo
Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.
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公开(公告)号：US12094552B2
公开(公告)日：2024-09-17
申请号：US18374026
申请日：2023-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan Park , Jinyoung Kim , Ilhan Park , Kyoman Kang , Sangwan Nam
CPC classification number: G11C29/50004 , G11C7/1039 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/18 , G11C16/28 , G11C29/44 , G11C2029/1202 , G11C2029/1204
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US12039186B2
公开(公告)日：2024-07-16
申请号：US17875569
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suyong Kim , Junyong Park , Sangbum Yun , Ilhan Park
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0679
Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.
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公开(公告)号：US20220180957A1
公开(公告)日：2022-06-09
申请号：US17368460
申请日：2021-07-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younghwi Yang , Ilhan Park , Jinyoung Kim , Sehwan Park , Dongmin Shin
Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.
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Patent Agency Ranking
公开(公告)号：US11972111B2
公开(公告)日：2024-04-30
申请号：US18052350
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyong Park , Minseok Kim , Jisu Kim , Ilhan Park , Doohyun Kim
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0679
Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.
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公开(公告)号：US11869579B2
公开(公告)日：2024-01-09
申请号：US17530911
申请日：2021-11-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Inho Kang , Ilhan Park , Jinyoung Chun
IPC: G11C11/4093 , G11C11/406 , G11C7/10 , G11C11/4096 , G11C11/4074 , G11C11/4094
CPC classification number: G11C11/4093 , G11C7/1039 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C11/40615
Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.
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公开(公告)号：US11682467B2
公开(公告)日：2023-06-20
申请号：US17353583
申请日：2021-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyoung Kim , Sehwan Park , Youngdeok Seo , Ilhan Park
CPC classification number: G11C29/42 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3495 , G11C29/4401
Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.
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公开(公告)号：US20230146741A1
公开(公告)日：2023-05-11
申请号：US18052350
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyong Park , Minseok Kim , Jisu Kim , Ilhan Park , Doohyun Kim
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0679
Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.
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公开(公告)号：US20230143341A1
公开(公告)日：2023-05-11
申请号：US17875569
申请日：2022-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suyong Kim , Junyong Park , Sangbum Yun , Ilhan Park
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0679
Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.
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