Memory controller, memory device and storage device

    公开(公告)号:US11556415B2

    公开(公告)日:2023-01-17

    申请号:US17397321

    申请日:2021-08-09

    Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.

    Method of testing a suspend operation

    公开(公告)号:US12039186B2

    公开(公告)日:2024-07-16

    申请号:US17875569

    申请日:2022-07-28

    CPC classification number: G06F3/0653 G06F3/0604 G06F3/0679

    Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

    Memory device for improving speed of program operation and operating method thereof

    公开(公告)号:US11972111B2

    公开(公告)日:2024-04-30

    申请号:US18052350

    申请日:2022-11-03

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0679

    Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

    MEMORY DEVICE FOR IMPROVING SPEED OF PROGRAM OPERATION AND OPERATING METHOD THEREOF

    公开(公告)号:US20230146741A1

    公开(公告)日:2023-05-11

    申请号:US18052350

    申请日:2022-11-03

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0679

    Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

    METHOD OF TESTING A SUSPEND OPERATION
    10.
    发明公开

    公开(公告)号:US20230143341A1

    公开(公告)日:2023-05-11

    申请号:US17875569

    申请日:2022-07-28

    CPC classification number: G06F3/0653 G06F3/0604 G06F3/0679

    Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

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