公开(公告)号：US20160247552A1

公开(公告)日：2016-08-25

申请号：US15000319

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Hyung KIM ,  In Young PARK ,  Dong Yoon SEO ,  Jong Hyun SEOK ,  Young Ho LEE ,  Dong Min JANG

IPC: G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4076

Abstract: A memory module includes a first printed circuit board (PCB) which includes a first surface, a second surface, first taps formed on the first surface, and second taps formed on the second surface, a first buffer attached to the first PCB, and first memory devices attached to the first PCB, in which the first buffer is configured to transmit signals input through the first taps and the second taps to the first memory devices, and signals re-driven by the first buffer among the signals are transmitted to a second module through the second taps.

Abstract translation: 存储器模块包括第一印刷电路板（PCB），其包括第一表面，第二表面，形成在第一表面上的第一抽头和形成在第二表面上的第二抽头，附接到第一PCB的第一缓冲器，以及第一印刷电路板 附接到第一PCB的存储器件，其中第一缓冲器被配置为将通过第一抽头输入的信号和第二抽头传送到第一存储器件，并且由信号中的第一缓冲器重新驱动的信号被传输到第二 模块通过第二个水龙头。

公开(公告)号：US20130313714A1

公开(公告)日：2013-11-28

申请号：US13837891

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Hyun SEOK ,  Do Hyung KIM ,  Kwang Seop KIM

IPC: H01L23/50

CPC classification number: H01L23/50 ,  G11C5/04 ,  G11C5/063 ,  H01L27/1052 ,  H01L2924/0002 ,  H05K1/0248 ,  H01L2924/00

Abstract: A semiconductor includes a first signal line commonly connected to a plurality of semiconductor devices and a second signal line commonly connected to one or more of the plurality of semiconductor devices. The first signal line has a first impedance per unit length, the second signal line has a second impedance per unit length, the second impedance per unit length is greater than the first impedance per unit length, and the first signal line has a longer routing length than the first signal line. Widths of the signal lines may be set to reduce a difference in the impedances.

Abstract translation: 半导体包括共同连接到多个半导体器件的第一信号线和共同连接到多个半导体器件中的一个或多个的第二信号线。 第一信号线具有每单位长度的第一阻抗，第二信号线具有每单位长度的第二阻抗，每单位长度的第二阻抗大于每单位长度的第一阻抗，并且第一信号线具有较长的路由长度 比第一条信号线。 可以设置信号线的宽度以减小阻抗的差异。