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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230371237A1

    公开(公告)日：2023-11-16

    申请号：US18226891

    申请日：2023-07-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun Young LEE ,  Do Hyung KIM ,  Taek Jung KIM ,  Seung Jong PARK ,  Jae Wha PARK ,  Youn Jae CHO

    IPC: H10B12/00 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H10B12/315 ,  H01L23/528 ,  H01L23/53266 ,  H10B12/34 ,  H10N50/01

    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM COMPRISING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM COMPRISING THE SAME 审中-公开

    公开(公告)号：US20200182916A1

    公开(公告)日：2020-06-11

    申请号：US16420751

    申请日：2019-05-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Do Hyung KIM ,  Min Young KANG

    IPC: G01R19/165

    Abstract: A semiconductor device is provided and includes: a voltage sensing circuit configured to output first and second sensing voltages based on a target voltage applied thereto; and a comparing circuit configured to generate a monitoring output signal based on levels of the first and second sensing voltages, wherein the voltage sensing circuit includes: a first transistor including a gate to receive a reference bias voltage, a source connected to an input node, and a drain connected to one end of a first resistive element; a second transistor provided in a current mirror structure with the first transistor, and including a drain connected to a third resistive element; and a second resistive element connected to another end of the first resistive element, the first sensing voltage being provided to both ends of the second resistive element, and the second sensing voltage being provided to both ends of the third resistive element.

    MEMORY MODULE, MEMORY SYSTEM INCLUDING THE SAME, AND DATA STORAGE SYSTEM INCLUDING THE MEMORY MODULE
    3.
    发明申请
    MEMORY MODULE, MEMORY SYSTEM INCLUDING THE SAME, AND DATA STORAGE SYSTEM INCLUDING THE MEMORY MODULE 有权
    存储器模块，包括其的存储器系统和包括存储器模块的数据存储系统

    公开(公告)号：US20160247552A1

    公开(公告)日：2016-08-25

    申请号：US15000319

    申请日：2016-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Do Hyung KIM ,  In Young PARK ,  Dong Yoon SEO ,  Jong Hyun SEOK ,  Young Ho LEE ,  Dong Min JANG

    IPC: G11C11/4093 ,  G11C11/4076

    CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4076

    Abstract: A memory module includes a first printed circuit board (PCB) which includes a first surface, a second surface, first taps formed on the first surface, and second taps formed on the second surface, a first buffer attached to the first PCB, and first memory devices attached to the first PCB, in which the first buffer is configured to transmit signals input through the first taps and the second taps to the first memory devices, and signals re-driven by the first buffer among the signals are transmitted to a second module through the second taps.

    Abstract translation: 存储器模块包括第一印刷电路板（PCB），其包括第一表面，第二表面，形成在第一表面上的第一抽头和形成在第二表面上的第二抽头，附接到第一PCB的第一缓冲器，以及第一印刷电路板 附接到第一PCB的存储器件，其中第一缓冲器被配置为将通过第一抽头输入的信号和第二抽头传送到第一存储器件，并且由信号中的第一缓冲器重新驱动的信号被传输到第二 模块通过第二个水龙头。

    SEMICONDUCTOR DEVICE HAVING ENHANCED SIGNAL INTEGRITY
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING ENHANCED SIGNAL INTEGRITY 审中-公开
    具有增强信号完整性的半导体器件

    公开(公告)号：US20130313714A1

    公开(公告)日：2013-11-28

    申请号：US13837891

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong Hyun SEOK ,  Do Hyung KIM ,  Kwang Seop KIM

    IPC: H01L23/50

    CPC classification number: H01L23/50 ,  G11C5/04 ,  G11C5/063 ,  H01L27/1052 ,  H01L2924/0002 ,  H05K1/0248 ,  H01L2924/00

    Abstract: A semiconductor includes a first signal line commonly connected to a plurality of semiconductor devices and a second signal line commonly connected to one or more of the plurality of semiconductor devices. The first signal line has a first impedance per unit length, the second signal line has a second impedance per unit length, the second impedance per unit length is greater than the first impedance per unit length, and the first signal line has a longer routing length than the first signal line. Widths of the signal lines may be set to reduce a difference in the impedances.

    Abstract translation: 半导体包括共同连接到多个半导体器件的第一信号线和共同连接到多个半导体器件中的一个或多个的第二信号线。 第一信号线具有每单位长度的第一阻抗，第二信号线具有每单位长度的第二阻抗，每单位长度的第二阻抗大于每单位长度的第一阻抗，并且第一信号线具有较长的路由长度 比第一条信号线。 可以设置信号线的宽度以减小阻抗的差异。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220173108A1

    公开(公告)日：2022-06-02

    申请号：US17372880

    申请日：2021-07-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun Young LEE ,  Do Hyung KIM ,  Taek Jung KIM ,  Seung Jong PARK ,  Jae Wha PARK ,  Youn Jae CHO

    IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528

    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

    LAMINATION APPARATUS AND LAMINATION METHOD USING THE SAME
    6.
    发明申请
    LAMINATION APPARATUS AND LAMINATION METHOD USING THE SAME 审中-公开
    使用它的层压装置和层压方法

    公开(公告)号：US20160318293A1

    公开(公告)日：2016-11-03

    申请号：US15139996

    申请日：2016-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Do Hyung KIM ,  Dong-Hee HAN ,  Do-Wan KIM ,  Byeong-Cheol KIM ,  Hak Rae KIM ,  Jung Hun SUNG ,  Sung-Gwan WOO ,  Kyung Woon JANG ,  Chang Kyu CHUNG ,  Kyoung Hern HONG ,  Sung-Ju HWANG

    IPC: B32B37/14 ,  B32B37/12

    CPC classification number: B32B38/1866 ,  B32B37/12 ,  B32B38/1841 ,  B32B2309/68 ,  B32B2457/20 ,  G02F1/1303 ,  Y10T156/1002 ,  Y10T156/1028

    Abstract: Disclosed herein are a lamination apparatus which adheres substrates to a cover window having a curved surface and a lamination method using the same. The lamination apparatus includes a first jig on which a cover window is mounted, wherein a curved surface portion is formed in the cover window and a curvature center thereof is positioned behind the curved surface portion, a second jig on which a guide member is seated, wherein a substrate is mounted on the guide member and the guide member has a width greater than that of the substrate, and an interference member provided to interfere with both facing front surfaces of the guide member, wherein the interference member interferes with the guide member and the guide member is bent when the second jig approaches the first jig.

    Abstract translation: 本文公开了一种层压装置，其将基板粘附到具有弯曲表面的盖窗口和使用其的层压方法。 层压装置包括：第一夹具，其上安装有盖窗，其中在所述盖窗中形成弯曲表面部分，并且其曲率中心位于所述弯曲表面部分的后面;第二夹具，其上安置有引导构件， 其中，基板被安装在所述引导构件上，并且所述引导构件具有大于所述基板的宽度的宽度，以及设置成干涉所述引导构件的两个相对的前表面的干涉构件，其中所述干涉构件干涉所述引导构件， 当第二夹具接近第一夹具时，引导构件弯曲。

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