Abstract:
A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.
Abstract:
Generating a random permutation by arranging a sequence N numbers in a matrix, performing random arrangement operations on the rows of the matrix to generate an intermediary matrix, performing random arrangement operations on the columns of the intermediary matrix to generate a second intermediary matrix, and arranging the N numbers of the second intermediary matrix as a rearranged sequence of the N numbers.
Abstract:
An embodiment includes an electronic device, comprising: a control intellectual property (IP) including a plurality of first special function registers (SFRs); a basic operation IP including a plurality of second SFRs and coupled to the control IP through a first path and a second path; and a random number generator configured to generate a random signal; wherein the control IP is configured to: select one of the first path and the second path based on the random signal; and set the second SFRs using the selected path.