公开(公告)号：US20190042765A1

公开(公告)日：2019-02-07

申请号：US16023401

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin CHUNG ,  Jae-Chul PARK ,  Ki-Seok BAE ,  Jong-Hoon SHIN ,  Yun-Ho YOUM ,  Hye-Soo LEE ,  Hong-Mook CHOI ,  Jin-Su HYUN

IPC: G06F21/60 ,  G06F21/78 ,  G06F21/85 ,  G06F21/57 ,  H04L9/06

Abstract: A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

公开(公告)号：US20130259224A1

公开(公告)日：2013-10-03

申请号：US13759476

申请日：2013-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ki LEE ,  Hong-Mook CHOI ,  Jong-Hoon SHIN

IPC: G06F7/58 ,  H04L9/28

CPC classification number: G06F7/582 ,  G06F7/766 ,  H04L9/0631 ,  H04L2209/08 ,  H04L2209/24

Abstract: Generating a random permutation by arranging a sequence N numbers in a matrix, performing random arrangement operations on the rows of the matrix to generate an intermediary matrix, performing random arrangement operations on the columns of the intermediary matrix to generate a second intermediary matrix, and arranging the N numbers of the second intermediary matrix as a rearranged sequence of the N numbers.

Abstract translation: 通过在矩阵中排列序列N个数来生成随机排列，对矩阵的行执行随机排列操作以生成中间矩阵，对中间矩阵的列执行随机排列操作以生成第二中间矩阵，并且布置 作为N个数的重排顺序的第二中间矩阵的N个数。

公开(公告)号：US20170344759A1

公开(公告)日：2017-11-30

申请号：US15488639

申请日：2017-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-Mook CHOI ,  Yun-Ho YOUM ,  Sang-Hyun PARK ,  Hyesoo LEE

IPC: G06F21/72 ,  G06F1/06

CPC classification number: G06F21/72 ,  G06F1/06 ,  G09C1/00 ,  H04L9/003 ,  H04L2209/12

Abstract: An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.

公开(公告)号：US20130297948A1

公开(公告)日：2013-11-07

申请号：US13718382

申请日：2012-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Soo LEE ,  Hong-Mook CHOI ,  Sang-Hyun PARK

IPC: G06F21/60

CPC classification number: G06F21/72 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/28 ,  G06F21/602 ,  G06F21/74 ,  G06F21/85 ,  G06F2206/1014 ,  H04L9/0822 ,  H04L2209/12

Abstract: A method of operating a system on chip (SoC) includes converting plain data into cipher data by using an encryption key and transmitting the cipher data directly to a memory controller which controls an operation of a non-volatile memory. The encryption key may be output by a one-time programmable (OTP) memory.

公开(公告)号：US20160112194A1

公开(公告)日：2016-04-21

申请号：US14291665

申请日：2014-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-Mook CHOI ,  Xingguang FENG

IPC: H04L9/10 ,  G06F1/10

CPC classification number: H04L9/00 ,  H04L9/003 ,  H04L9/0625 ,  H04L2209/12 ,  H04L2209/122 ,  H04L2209/127

Abstract: Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.

Abstract translation: 提供了一种使用多对一二进制功能实现加密算法的S-Box的加密设备。 密码装置包括：第一逻辑门阵列，包括I个第一逻辑门，每个第一逻辑门接收输入信号的2位; 2N个第二逻辑门，每个第二逻辑门从从第一逻辑门的阵列输出的I位中接收相应的J位; 和L个第三逻辑门，每个逻辑门从第二逻辑门输出的2N位中接收K位，其中在输入信号的N位和输入到每个第三逻辑的K位之间存在多对一的对应关系 门，并且其中N，I，J，K和L是正整数。 因为每个阵列的信号输出仅包含一个有效位，所以电流始终被消耗，以防止内部数据泄漏到黑客中。

公开(公告)号：US20150254476A1

公开(公告)日：2015-09-10

申请号：US14577608

申请日：2014-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Ki LEE ,  Yun-Ho YOUM ,  Hong-Mook CHOI ,  Jinsu HYUN ,  KeeMoon CHUN

IPC: G06F21/72

CPC classification number: G06F21/72 ,  G06F21/556 ,  G09C1/00 ,  H04L9/003 ,  H04L2209/34

Abstract: A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Abstract translation: 提供了一种编码方法和编码器。 该方法包括使用输入单热位产生用于最高有效位（MSB）的第一单热位和用于最低有效位（LSB）的第一单热位; 通过使用交叉连接的第一逻辑运算将第一单热比特编码到MSB和互补MSB; 以及通过使用交叉连接的第二逻辑运算将第二单热比特编码到LSB和互补LSB。 编码器包括第一位发生器，第一编码器，第二位发生器和第二编码器。