公开(公告)号：US10770154B2

公开(公告)日：2020-09-08

申请号：US16294058

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Heon Yu ,  Joung Yeal Kim ,  Chul Ung Kim ,  Hyun Bo Kim ,  Joo Youn Lim

IPC: G11C11/406 ,  G11C5/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/20

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

公开(公告)号：US20200082889A1

公开(公告)日：2020-03-12

申请号：US16294058

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Heon Yu ,  Joung Yeal Kim ,  Chul Ung Kim ,  Hyun Bo Kim ,  Joo Youn Lim

IPC: G11C16/34 ,  G11C16/20 ,  G11C16/16 ,  G11C16/08

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

公开(公告)号：US20130322150A1

公开(公告)日：2013-12-05

申请号：US13803336

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Hoon Kim ,  Joung Yeal Kim ,  Se Il Oh

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a memory cell array, a column decoder, and a row decoder. The memory cell array includes a plurality of antifuse memory cells arranged in rows and columns, each of the antifuse memory cells connected to one of a plurality of word lines, one of a plurality of high-voltage lines, and one of a plurality of bit lines. The column decoder is arranged at a first side of the memory cell array and configured to select one bit line among the bit lines. The row decoder is arranged parallel to the column decoder in a first direction, and configured to select one word line among the word lines.

Abstract translation: 存储器件包括存储单元阵列，列解码器和行解码器。 存储单元阵列包括排列成行和列的多个反熔丝存储单元，每个反熔丝存储单元连接到多个字线中的一个，多个高压线之一和多个位中的一个 线条。 列解码器被布置在存储单元阵列的第一侧，并且被配置为在位线中选择一个位线。 行解码器在第一方向上平行于列解码器布置，并且被配置为在字线中选择一个字线。