公开(公告)号：US10923181B2

公开(公告)日：2021-02-16

申请号：US16248004

申请日：2019-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Ho Jeon ,  Hun-Dae Choi

IPC: G11C11/4093 ,  G11C11/4094 ,  H03K19/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

公开(公告)号：US10573401B2

公开(公告)日：2020-02-25

申请号：US16030125

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Seok Heo ,  Jung Hwan Choi ,  Wang Soo Kim ,  Yoo Chang Sung ,  Jun Ha Lee ,  Ju Ho Jeon

IPC: G11C29/36 ,  G11C29/26 ,  G11C11/408 ,  G11C29/12 ,  G11C11/4093 ,  G11C29/38 ,  G11C29/18 ,  H01L25/065

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

公开(公告)号：US20200027498A1

公开(公告)日：2020-01-23

申请号：US16248004

申请日：2019-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Ho Jeon ,  Hun-Dae Choi

IPC: G11C11/4093 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  H03K19/00

Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.