公开(公告)号：US10573401B2

公开(公告)日：2020-02-25

申请号：US16030125

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Seok Heo ,  Jung Hwan Choi ,  Wang Soo Kim ,  Yoo Chang Sung ,  Jun Ha Lee ,  Ju Ho Jeon

IPC: G11C29/36 ,  G11C29/26 ,  G11C11/408 ,  G11C29/12 ,  G11C11/4093 ,  G11C29/38 ,  G11C29/18 ,  H01L25/065

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

公开(公告)号：US12111680B2

公开(公告)日：2024-10-08

申请号：US17871374

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Hyun Kwon ,  Min-Hyeong Kim ,  Wang Soo Kim

IPC: G06F1/08 ,  H04L25/03

CPC classification number: G06F1/08 ,  H04L25/03057

Abstract: A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.