公开(公告)号：US20220262793A1

公开(公告)日：2022-08-18

申请号：US17731316

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Gi Gwan PARK

IPC: H01L27/088 ,  H01L29/78 ,  H01L49/02 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.

公开(公告)号：US20190019794A1

公开(公告)日：2019-01-17

申请号：US16117065

申请日：2018-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Gi Gwan PARK

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/11 ,  H01L49/02

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.

公开(公告)号：US20180211887A1

公开(公告)日：2018-07-26

申请号：US15928858

申请日：2018-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Ji Hwan AN ,  Tae Won HA ,  Se Ki HONG

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

公开(公告)号：US20200058652A1

公开(公告)日：2020-02-20

申请号：US16290222

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo PARK ,  Ju Youn KIM ,  Hyung Joo NA ,  Sang Min YOO ,  Eui Chul HWANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

公开(公告)号：US20200043920A1

公开(公告)日：2020-02-06

申请号：US16382382

申请日：2019-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min YOO ,  Ju Youn KIM ,  Hyung Joo NA ,  Bong Seok SUH ,  Joo Ho JUNG ,  Eui Chul HWANG ,  Sung Moon LEE

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L29/40

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

公开(公告)号：US20190131417A1

公开(公告)日：2019-05-02

申请号：US15958061

申请日：2018-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Ki HONG ,  Ju Youn KIM ,  Jin-Wook KIM ,  Tae Eung YOON ,  Tae Won HA ,  Jung Hoon SEO ,  Seul Gi YUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.

公开(公告)号：US20200006341A1

公开(公告)日：2020-01-02

申请号：US16244324

申请日：2019-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Ki HONG ,  Ju Youn KIM ,  Jin Wook KIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.

公开(公告)号：US20190214388A1

公开(公告)日：2019-07-11

申请号：US16238988

申请日：2019-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn KIM ,  Se Ki Hong

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L29/42376 ,  H01L29/4966

Abstract: A semiconductor device includes a substrate including a first area and a second area, and first and second transistors formed in the first area and the second area, respectively. The first transistor includes a first gate insulating layer on the substrate, a first TiN layer on the first gate insulating layer contacting the first gate insulating layer, and a first filling layer on the first TiN layer. The second transistor includes a second gate insulating layer on the substrate, a second TiN layer on the second gate insulating layer contacting the second gate insulating layer, and a second filling layer on the second TiN layer. A threshold voltage of the first transistor is less than that of the second transistor, the second gate insulating layer does not comprise lanthanum, and an oxygen content of a portion of the first TiN layer is greater than that of the second TiN layer.

公开(公告)号：US20180358450A1

公开(公告)日：2018-12-13

申请号：US15842050

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn KIM

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, source/drain regions on the fin, a recess between the source/drain regions, a device isolation region including a capping layer extending along an inner surface of the recess and a device isolating layer on the capping layer to fill the recess, a dummy gate structure on the device isolation region and including a dummy gate insulating layer, outer spacers on opposite sidewalls of the dummy gate structure, first inner spacers between the dummy gate structure and the outer spacers, and a second inner spacer between the device isolation region and the dummy gate insulating layer.

公开(公告)号：US20180301383A1

公开(公告)日：2018-10-18

申请号：US15844534

申请日：2017-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn KIM

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A substrate has an NMOS region and a PMOS region. A first gate electrode structure is disposed on the NMOS region of the substrate. The first gate electrode structure includes a first barrier layer, a first gate electrode layer and a second barrier layer stacked as listed. A second gate electrode structure is disposed on the PMOS region. The second gate electrode structure includes a third barrier layer, a second gate electrode layer and a third gate electrode layer stacked as listed. The first gate electrode layer and the third gate electrode layer include substantially the same material. The second barrier layer and the second gate electrode layer include substantially the same material.