公开(公告)号：US20240274540A1

公开(公告)日：2024-08-15

申请号：US18647307

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Dongbeen KIM ,  Jinwook KIM ,  Juhun PARK ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM

IPC: H01L23/535 ,  H01L23/00 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L24/13 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2224/13025

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

公开(公告)号：US20220336357A1

公开(公告)日：2022-10-20

申请号：US17521080

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Dongbeen KIM ,  Jinwook KIM ,  Juhun PARK ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/00 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

公开(公告)号：US20220157955A1

公开(公告)日：2022-05-19

申请号：US17469361

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun PARK ,  Deokhan BAE ,  Jin-Wook KIM ,  Yuri LEE ,  Inyeal LEE ,  Yoonyoung JUNG

IPC: H01L29/417 ,  H01L27/092 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

公开(公告)号：US20220131008A1

公开(公告)日：2022-04-28

申请号：US17569952

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan BAE ,  Juhun PARK ,  Myungyoon UM ,  Kwangyong JANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US20190148384A1

公开(公告)日：2019-05-16

申请号：US15983405

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan BAE ,  Hyonwook RA ,  Hyung Jong LEE ,  Juhun PARK

IPC: H01L27/11 ,  G11C11/412 ,  H01L23/522

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

公开(公告)号：US20220375934A1

公开(公告)日：2022-11-24

申请号：US17569795

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun PARK ,  Deokhan BAE ,  Myungyoon UM ,  Yuri LEE ,  Yoonyoung JUNG ,  Sooyeon HONG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

公开(公告)号：US20210305427A1

公开(公告)日：2021-09-30

申请号：US17028191

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan BAE ,  Juhun PARK ,  Myungyoon UM ,  Kwangyong JANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.