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    Semiconductor devices including unitary supports
    2.
    发明授权
    Semiconductor devices including unitary supports 有权
    半导体器件包括单一支撑

    公开(公告)号：US09087729B2

    公开(公告)日：2015-07-21

    申请号：US14336334

    申请日：2014-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Oh Park ,  Chang-Hwan Kim ,  Whan Namkoong ,  Jun-Young Jang

    IPC: H01L27/108 ,  H01L23/00 ,  H01L49/02

    CPC classification number: H01L27/10814 ,  H01L24/14 ,  H01L27/10808 ,  H01L27/10855 ,  H01L28/90 ,  H01L2224/1401 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/14151 ,  H01L2224/1451 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

    Abstract: A semiconductor device includes a plurality of cylindrical structures located at vertices and central points of a plurality of hexagons in a honeycomb pattern, and a unitary support having a plurality of openings. Each of the openings exposes a part each of four of the cylindrical structures. Each of the openings has the shape of a parallelogram or an oval substantially. A first distance between opposite cylindrical structures of a first pair of the four cylindrical structures exposed by each opening is shorter than a second distance between opposite cylindrical structures of a second pair of the four cylindrical structures exposed by the opening. The first distance is equal to a distance between the central point and each of the vertices of the hexagon.

    Abstract translation: 半导体器件包括位于蜂窝状图案的多个六边形的顶点和中心点处的多个圆柱形结构，以及具有多个开口的单一支撑件。 每个开口暴露四个圆柱形结构中的每一个的一部分。 每个开口都具有平行四边形或椭圆形的形状。 由每个开口暴露的第一对四个圆柱形结构的相对的圆柱形结构之间的第一距离比通过开口暴露的第四对圆柱形结构的第二对的圆柱形结构之间的第二距离短。 第一个距离等于六边形的中心点和每个顶点之间的距离。

    Device controller that schedules memory access to a host memory, and storage device including the same
    3.
    发明授权
    Device controller that schedules memory access to a host memory, and storage device including the same 有权

    公开(公告)号：US10782915B2

    公开(公告)日：2020-09-22

    申请号：US16058197

    申请日：2018-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seon-Bong Kim ,  Jun-Young Jang ,  Jong-Hwan Kim ,  Ho-Jun Shim

    IPC: G06F3/06

    Abstract: A device controller included in a storage device includes a host controller connected to a host memory, a memory controller connected to a plurality of nonvolatile memory devices, a protocol controller configured to control data transfer between the host controller and the plurality of nonvolatile memory devices, and to perform data memory access to a data region of the host memory and non-data memory access to a non-data region of the host memory through the host controller, and a scheduler configured to re-order the data memory access and the non-data memory access such that the non-data memory access to the non-data region is performed after the data memory access to a data chunk has completed, the data chunk being successive data that is allocated within the data region by a physical region page (PRP).

    DEVICE CONTROLLER THAT SCHEDULES MEMORY ACCESS TO A HOST MEMORY, AND STORAGE DEVICE INCLUDING THE SAME
    4.
    发明申请
    DEVICE CONTROLLER THAT SCHEDULES MEMORY ACCESS TO A HOST MEMORY, AND STORAGE DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190155545A1

    公开(公告)日：2019-05-23

    申请号：US16058197

    申请日：2018-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seon-Bong Kim ,  Jun-Young Jang ,  Jong-Hwan Kim ,  Ho-Jun Shim

    IPC: G06F3/06

    Abstract: A device controller included in a storage device includes a host controller connected to a host memory, a memory controller connected to a plurality of nonvolatile memory devices, a protocol controller configured to control data transfer between the host controller and the plurality of nonvolatile memory devices, and to perform data memory access to a data region of the host memory and non-data memory access to a non-data region of the host memory through the host controller, and a scheduler configured to re-order the data memory access and the non-data memory access such that the non-data memory access to the non-data region is performed after the data memory access to a data chunk has completed, the data chunk being successive data that is allocated within the data region by a physical region page (PRP).

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