公开(公告)号：US20230378068A1

公开(公告)日：2023-11-23

申请号：US18098986

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGHOO SHIN ,  SANGHYUN LEE ,  KOUNGMIN RYU ,  JONGMIN BAEK ,  KYUNGYUB JEON ,  KYU-HEE HAN

IPC: H01L23/532 ,  H01L27/092 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L23/5226

Abstract: A semiconductor device may include PMOSFET and NMOSFET regions spaced apart from each other on a substrate, first and second active patterns provided on the PMOSFET and NMOSFET regions, respectively, a first channel pattern on the first active pattern, a source/drain pattern electrically connected to the first channel pattern, an active contact electrically connected to the source/drain pattern, the active contact including a first conductive pattern and a first barrier pattern enclosing a portion of a side surface and a bottom surface of the first conductive pattern, a gate electrode extending in a direction crossing the first channel pattern, a gate contact electrically connected to the gate electrode, an air gap provided on the first barrier pattern and between the gate contact and the first conductive pattern, and a lower via provided on the active contact. The lower via may be adjacent to the air gap.

公开(公告)号：US20230072817A1

公开(公告)日：2023-03-09

申请号：US17849797

申请日：2022-06-27

Applicant: Samsung Electronics Co, Ltd.

Inventor： JUNGHWAN CHUN ,  HONGSIK SHIN ,  KOUNGMIN RYU ,  BONGKWAN BAEK ,  JONGMIN BAEK

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.