公开(公告)号：US20230378068A1

公开(公告)日：2023-11-23

申请号：US18098986

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGHOO SHIN ,  SANGHYUN LEE ,  KOUNGMIN RYU ,  JONGMIN BAEK ,  KYUNGYUB JEON ,  KYU-HEE HAN

IPC: H01L23/532 ,  H01L27/092 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L23/5226

Abstract: A semiconductor device may include PMOSFET and NMOSFET regions spaced apart from each other on a substrate, first and second active patterns provided on the PMOSFET and NMOSFET regions, respectively, a first channel pattern on the first active pattern, a source/drain pattern electrically connected to the first channel pattern, an active contact electrically connected to the source/drain pattern, the active contact including a first conductive pattern and a first barrier pattern enclosing a portion of a side surface and a bottom surface of the first conductive pattern, a gate electrode extending in a direction crossing the first channel pattern, a gate contact electrically connected to the gate electrode, an air gap provided on the first barrier pattern and between the gate contact and the first conductive pattern, and a lower via provided on the active contact. The lower via may be adjacent to the air gap.

公开(公告)号：US20170084493A1

公开(公告)日：2017-03-23

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGWOO HAN ,  KWANG-YONG YANG ,  JINWOOK LEE ,  KYUNGYUB JEON ,  HAEGEON JUNG ,  DOHYOUNG KIM

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US20180240710A1

公开(公告)日：2018-08-23

申请号：US15959319

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGWOO HAN ,  KWANG-YONG YANG ,  JINWOOK LEE ,  KYUNGYUB JEON ,  HAEGEON JUNG ,  DOHYOUNG KIM

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.