公开(公告)号：US11004732B2

公开(公告)日：2021-05-11

申请号：US16454860

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US10128241B2

公开(公告)日：2018-11-13

申请号：US15878990

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo Kim ,  Koung-min Ryu

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.

公开(公告)号：US10381265B2

公开(公告)日：2019-08-13

申请号：US15589169

申请日：2017-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US20190318961A1

公开(公告)日：2019-10-17

申请号：US16454860

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US20180166443A1

公开(公告)日：2018-06-14

申请号：US15878990

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo Kim ,  Koung-min Ryu

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/53209 ,  H01L29/66545 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.