公开(公告)号：US20210043240A1

公开(公告)日：2021-02-11

申请号：US16916345

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US11763869B2

公开(公告)日：2023-09-19

申请号：US17549095

申请日：2021-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US11200932B2

公开(公告)日：2021-12-14

申请号：US16916345

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US12300355B2

公开(公告)日：2025-05-13

申请号：US18235189

申请日：2023-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

IPC: G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US20250123962A1

公开(公告)日：2025-04-17

申请号：US18744826

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjin Choi ,  Sunghyun Noh ,  Hyuk Lee ,  Kuiyon Mun

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/40

Abstract: A method of operating a storage device including a nonvolatile memory device and a storage controller that is configured to control the nonvolatile memory device, the method comprising: partitioning the nonvolatile memory device into a plurality of domains; determining a scramble function based on a seed value of seed bits that correspond to a first portion of a plurality of address bits of a logical address among a plurality of logical addresses that are provided from a host device; generating a scrambled domain value based on the scramble function and a domain value of domain bits that correspond to a second portion of the plurality of address bits of the logical address among the plurality of logical addresses; and assigning a write operation that corresponds to the logical address to a domain that corresponds to the scrambled domain value among the plurality of domains.