公开(公告)号：US20240064979A1

公开(公告)日：2024-02-22

申请号：US18142191

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jun Park ,  Kyung Hyun Kim ,  Kun-Woo Park ,  Jun-Youl Yang ,  Dong Woo Lee ,  Sang Hyuk Hong

IPC: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/065

CPC classification number: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/0652

Abstract: A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.