公开(公告)号：US09893077B2

公开(公告)日：2018-02-13

申请号：US15049160

申请日：2016-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong Hoon Son ,  Kyung Hyun Kim ,  Byeong Ju Kim ,  Kwang Chul Park ,  Yeon Sil Sohn ,  Jin I Lee ,  Jong Heun Lim ,  Won Bong Jung

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36 ,  H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/1157 ,  H01L21/02 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/02667 ,  H01L21/02675 ,  H01L27/11573 ,  H01L27/11582

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

公开(公告)号：US20240064979A1

公开(公告)日：2024-02-22

申请号：US18142191

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jun Park ,  Kyung Hyun Kim ,  Kun-Woo Park ,  Jun-Youl Yang ,  Dong Woo Lee ,  Sang Hyuk Hong

IPC: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/065

CPC classification number: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/0652

Abstract: A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.