公开(公告)号：US11381231B2

公开(公告)日：2022-07-05

申请号：US16989074

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob Chae ,  Jong-Ryun Choi

IPC: H03K5/156 ,  H03K5/133 ,  G01R31/317 ,  H03K5/135

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

公开(公告)号：US09864720B2

公开(公告)日：2018-01-09

申请号：US15264946

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob Chae ,  Hyun-Hyuck Kim ,  Sang Hune Park ,  Shin Young Yi ,  Won Lee

IPC: G11C7/00 ,  G06F13/42 ,  G11C7/22

CPC classification number: G06F13/4243 ,  G11C7/22

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.