公开(公告)号：US09954057B2

公开(公告)日：2018-04-24

申请号：US15424406

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Jae Song ,  Jae-Hyun Yoo ,  In-Hack Lee ,  Seong-Hun Jang ,  Myoung-Kyu Park ,  Young-Mok Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L21/266 ,  H01L21/308 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L21/266 ,  H01L21/308 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/7833

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

公开(公告)号：US09324832B1

公开(公告)日：2016-04-26

申请号：US14856666

申请日：2015-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Hyun Baek ,  Kwan-Jae Song ,  Jong-Sung Jeon

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract translation: 在一种方法中，在基板上形成伪栅极层结构和掩模层。 将掩模层图案化以形成掩模。 垫片形成在面罩的侧壁上。 在间隔件之间形成虚拟栅极掩模。 使用伪栅极掩模对虚拟栅极层结构进行图案化以形成伪栅极结构。 虚拟栅极结构被栅极结构代替。 当形成掩模时，设计沿第一方向延伸的掩模的初始布局。 针对初始布局的特定区域提供第二方向上的偏移偏移，以设计沿着第一方向具有沿第二方向的宽度变化的最终布局。 根据最终布局图案化掩模层以形成具有沿着第一方向变化的宽度的掩模。