公开(公告)号：US09548401B2

公开(公告)日：2017-01-17

申请号：US14698909

申请日：2015-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Su-Tae Kim ,  Byeong-Ryeol Lee ,  Seong-Hun Jang ,  Jong-Sung Jeon

IPC: H01L29/02 ,  H01L29/94 ,  H01L29/78 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7838 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract translation: 一种半导体器件包括：衬底，其包括具有第一掺杂浓度的第一杂质扩散区域和具有不同于第一掺杂浓度的第二掺杂浓度的至少一个第二杂质扩散区域，所述至少一个第二杂质区域被第一杂质包围 扩散区; 面向所述第一杂质扩散区域和所述至少一个第二杂质扩散区域的至少一个电极; 以及在所述第一杂质扩散区域和所述至少一个电极之间以及所述至少一个第二杂质扩散区域和所述至少一个电极之间的至少一个绝缘层。

公开(公告)号：US09954057B2

公开(公告)日：2018-04-24

申请号：US15424406

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Jae Song ,  Jae-Hyun Yoo ,  In-Hack Lee ,  Seong-Hun Jang ,  Myoung-Kyu Park ,  Young-Mok Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L21/266 ,  H01L21/308 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L21/266 ,  H01L21/308 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/7833

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.