公开(公告)号：US20240196603A1

公开(公告)日：2024-06-13

申请号：US18508445

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee CHEON ,  Hyukwoo KWON ,  Munjun KIM ,  Sungyeon KIM ,  Younseok CHOI

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/488 ,  H01L29/4236 ,  H10B12/50

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined by a device isolation trench, a device isolation structure including an etching induction film and filling the device isolation trench, the etching induction film covering a bottom surface of the device isolation trench, a word line trench intersecting with the plurality of active regions and the device isolation structure and extending in a first lateral direction, a gate dielectric film covering an inner wall of the word line trench, and a word line filling a portion of the word line trench on the gate dielectric film, wherein each of the plurality of active regions includes a fin body portion under the word line and a saddle fin portion protruding from the fin body portion toward the word line, and the etching induction film is exposed by the word line trench.

公开(公告)号：US20230276611A1

公开(公告)日：2023-08-31

申请号：US18102897

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo CHUNG ,  Chanmi LEE ,  Hayoung YI ,  Kwanghee CHEON ,  Seunghee HAN

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/02 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of reference patterns and a peripheral pattern on a feature layer by using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns; forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns by using a second material; removing the plurality of reference patterns; forming a plurality of second spacers on both sidewalls of each of the plurality of first spacers by using the first material; removing the plurality of first spacers so that the plurality of second spacers and the peripheral pattern remain on the feature layer; and patterning the feature layer by using the plurality of second spacers and the peripheral pattern as an etch mask.