公开(公告)号：US20230276611A1

公开(公告)日：2023-08-31

申请号：US18102897

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo CHUNG ,  Chanmi LEE ,  Hayoung YI ,  Kwanghee CHEON ,  Seunghee HAN

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/02 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of reference patterns and a peripheral pattern on a feature layer by using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns; forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns by using a second material; removing the plurality of reference patterns; forming a plurality of second spacers on both sidewalls of each of the plurality of first spacers by using the first material; removing the plurality of first spacers so that the plurality of second spacers and the peripheral pattern remain on the feature layer; and patterning the feature layer by using the plurality of second spacers and the peripheral pattern as an etch mask.

公开(公告)号：US20240297051A1

公开(公告)日：2024-09-05

申请号：US18407536

申请日：2024-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo CHUNG ,  Seunghee HAN ,  Seulgi LEE ,  Chanmi LEE

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/31116

Abstract: A method for manufacturing a semiconductor device includes stacking an etch target layer and an etching mask layer on a substrate having first through third regions, forming first photoresist patterns on the etching mask layer in the first and second regions and a second photoresist pattern to completely cover the third mask layer in the third region, etching the etching mask layer using the first and second photoresist patterns as etching masks to form first mask patterns on the first and second regions and a second mask pattern on the third region, forming a filling pattern in a first opening between first mask patterns on the second region, etching the etch target layer using the first and second mask patterns and the filling pattern as etching masks to form first patterns including second openings on the first region and a bulk pattern covering second and third regions of the substrate.

公开(公告)号：US20190287975A1

公开(公告)日：2019-09-19

申请号：US16422054

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Joonkyu RHEE ,  Ji-Hye Lee ,  Chanmi LEE ,  Taeseop CHOI

IPC: H01L27/108

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US20170271340A1

公开(公告)日：2017-09-21

申请号：US15405808

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Joonkyu RHEE ,  Ji-Hye LEE ,  Chanmi LEE ,  Taeseop CHOI

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.