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    METHODS OF FABRICATING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220336468A1

    公开(公告)日：2022-10-20

    申请号：US17858361

    申请日：2022-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Heon LEE ,  Munjun KIM ,  ByeongJu BAE

    IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/033

    Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

    INTEGRATED CIRCUIT DEVICES AND MANUFACTURING METHODS FOR THE SAME
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICES AND MANUFACTURING METHODS FOR THE SAME 有权

    公开(公告)号：US20210125884A1

    公开(公告)日：2021-04-29

    申请号：US16919307

    申请日：2020-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

    IPC: H01L23/29 ,  H01L21/02 ,  H01L23/31

    Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240196603A1

    公开(公告)日：2024-06-13

    申请号：US18508445

    申请日：2023-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwanghee CHEON ,  Hyukwoo KWON ,  Munjun KIM ,  Sungyeon KIM ,  Younseok CHOI

    IPC: H10B12/00 ,  H01L29/423

    CPC classification number: H10B12/488 ,  H01L29/4236 ,  H10B12/50

    Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined by a device isolation trench, a device isolation structure including an etching induction film and filling the device isolation trench, the etching induction film covering a bottom surface of the device isolation trench, a word line trench intersecting with the plurality of active regions and the device isolation structure and extending in a first lateral direction, a gate dielectric film covering an inner wall of the word line trench, and a word line filling a portion of the word line trench on the gate dielectric film, wherein each of the plurality of active regions includes a fin body portion under the word line and a saddle fin portion protruding from the fin body portion toward the word line, and the etching induction film is exposed by the word line trench.

    METHODS OF FABRICATING SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20170005099A1

    公开(公告)日：2017-01-05

    申请号：US15160264

    申请日：2016-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Heon LEE ,  Munjun KIM ,  ByeongJu BAE

    IPC: H01L27/108 ,  H01L21/687 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/3213

    Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

    Abstract translation: 制造半导体器件的方法包括在衬底中形成器件隔离层以限定有源区，在有源区上形成导电层，形成与导电层上的有源区相交的第一掩模图案，使用第一 掩模图案作为蚀刻掩模以形成位线，从第一掩模图案的顶表面生长第二掩模图案，以及使用第二掩模图案作为蚀刻掩模来执行图案化处理，以形成暴露位线之间的有源区域的接触孔。

    INTEGRATED CIRCUIT DEVICES
    9.
    发明申请
    INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220173002A1

    公开(公告)日：2022-06-02

    申请号：US17672939

    申请日：2022-02-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungheon LEE ,  Jaekang KOH ,  Hyukwoo KWON ,  Munjun KIM ,  Taejong HAN

    IPC: H01L23/29 ,  H01L23/31 ,  H01L21/02

    Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

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