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    Three-dimensional semiconductor memory device
    2.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11211402B2

    公开(公告)日：2021-12-28

    申请号：US16750176

    申请日：2020-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

    IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  G11C8/14

    Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190139979A1

    公开(公告)日：2019-05-09

    申请号：US16018199

    申请日：2018-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KOHJI KANAMORI ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C8/14

    CPC classification number: H01L27/11582 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

    Three-dimensional semiconductor memory device
    5.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10566345B2

    公开(公告)日：2020-02-18

    申请号：US16018199

    申请日：2018-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

    IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/14

    Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190172838A1

    公开(公告)日：2019-06-06

    申请号：US16108294

    申请日：2018-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwonsoon Jo ,  Seo-Goo Kang ,  Younghwan Son ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C7/14 ,  G11C7/18 ,  H01L23/532

    Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.

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